This article needs attention from an expert on the subject. The specific problem is: Still an issue regarding 10nm/7nm terminology that isn't addressed in the 10 nanometer and 7 nanometer is a deviation from the International Technology Roadmap for Semiconductors definitions. In short, 7 nm Samsung/TSMC is equivalent to 10 nm Intel. Thus treating 10 nm Intel and 7 nm Samsung/TSMC at different articles due to marketing material not real measurements seems to be incorrect, specially when the pages refer to ITRS roadmap (duplicate note at other affected article.
In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the 10 nanometer (10 nm) node as the technology node following the 14 nm node. "10 nm class" denotes chips made using process technologies between 10 and 20 nanometers.
All production "10 nm" processes are based on silicon CMOS finFET technology. Samsung first started their production of "10nm" chips in 2016; with product shipments following through in 2017 in the form of Galaxy S8.
The ITRS's original naming of this technology node was "11 nm". According to the 2007 edition of the roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a DRAM should be 11 nm.
In actuality, "10nm" as it is generally understood in 2018 is only in high-volume production at Samsung. GlobalFoundries has skipped 10nm, Intel has not yet started high-volume 10nm production, due to yield issues, and TSMC has considered 10nm to be a short-lived node, mainly dedicated to processors for Apple during 2017-2018, moving on to 7nm in 2018.
There is also a distinction to be made between 10nm as marketed by foundries and 10nm as marketed by DRAM companies.
On September 12, 2017, Apple announced the Apple A11, a 64-bit ARM-based system on a chip, manufactured by TSMC using a 10 nm FinFET process and containing 4.3 billion transistors on a die of 87.66 mm2.
In April 2018, Intel announced a delay in volume production of 10 nm mainstream CPUs until sometime in 2019. In July the exact time was further pinned down to the holiday season. In the meantime however, they did release a low-power 10nm mobile chip, albeit exclusive to Chinese markets.
|ITRS Logic Device
|TSMC||Samsung||ITRS Logic Device
|Process name||11/10 nm||10 nm
|10 nm||10 nm||16/14 nm|
|Transistor Gate Pitch (nm)||48||54||66||68||70|
|Interconnect pitch (nm)||36||36||44||51||56|
|Transistor Fin Pitch (nm)||36||34||36||42||42|
|Transistor Fin Height (nm)||42||53||Unknown||49||42|
Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch). Samsung reported their 10 nm process as having a 64 nm transistor gate pitch and 48 nm interconnect pitch. TSMC reported their 10 nm process as having a 64 nm transistor gate pitch and 42 nm interconnect pitch. Further investigation by Tech Insights revealed these values to be false and they have been updated accordingly. In addition, the transistor fin height of Samsung's 10 nm process was updated by MSSCORPS CO at SEMICON Taiwan 2017.
For the DRAM industry, the "10nm" node is often referred to as "10-nm class" and this dimension generally refers to the half-pitch of the active area. The "10nm" foundry structures are generally much larger. Samsung is also the most prominent player for 10nm-class DRAM.
Samsung 10LPE process
|CMOS manufacturing processes||Succeeded by|
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