In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the 10 nanometer (10 nm) node as the technology node following the 14 nm node. "10 nm class" denotes chips made using process technologies between 10 and 20 nanometers.
The ITRS's original naming of this technology node was "11 nm". According to the 2007 edition of the roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a DRAM should be 11 nm. Pat Gelsinger, at the time serving as Intel's Chief Technology Officer, claimed in 2008 that Intel saw a 'clear way' towards the 10 nm node. At the 11 nm node, Intel expected (in 2006) to be using a half-pitch of around 21 nm, in 2015, Nvidia's chief scientist, William Dally, claimed (in 2009) that they would also reach 11 nm semiconductors in 2015, a transition he claimed would be facilitated principally through new electronic design automation tools.
While the roadmap has been based on the continuing extension of CMOS technology, even this roadmap does not guarantee that silicon-based CMOS will extend that far. This is to be expected, since the gate length for this node may be smaller than 6 nm, and the corresponding gate dielectric thickness would scale down to a monolayer or even less. Scientists have estimated that transistors at these dimensions are significantly affected by quantum tunnelling. As a result, non-silicon extensions of CMOS, using III-V materials or carbon nanotube/nanowires, as well as non-CMOS platforms, including molecular electronics, spin-based computing, and single-electron devices, have been proposed. Hence, this node marks the practical beginning of nanoelectronics.
The extensive use of ultra-low-κ dielectrics (such as spin-on polymers or other porous materials) means that conventional photolithography, etch, or even chemical-mechanical polishing processes are unlikely to be used, because these materials contain a high density of voids and gaps. At the ~10 nm scale, quantum tunneling (especially through gaps) becomes a significant phenomenon. Controlling gaps on these scales by means of electromigration can produce interesting electrical properties.
Quantum tunneling may be advantageous if its effect on device behavior can be understood, and exploited, in the design. Future transistors may have insulating channels. An electron wave function decays exponentially in a "classically forbidden" region at a rate that can be controlled by the gate voltage. Interference effects are also possible; Alternate option is in heavier mass semiconducting channels. Photoemission electron microscopy (PEEM) data has been used to show that low energy electrons ~1.35 eV could travel as far as ~15 nm in SiO2, despite an average measured attenuation length of 1.18 nm.
In 2012, IBM produced a sub-10 nm carbon nanotube transistor that outperformed silicon on speed and power. "The superior low-voltage performance of the sub-10 nm CNT transistor proves the viability of nanotubes for consideration in future aggressively scaled transistor technologies," according to the abstract of the paper in Nano Letters.
As of mid-2016, semiconductor business Intel, and foundries at TSMC, and Samsung were all expected to ship or begin volume production of 10 nm devices in the first quarter of 2017, with foundry customers for 2017 including Qualcomm (Snapdragon 835) at Samsung, and Apple Inc. and MediaTek at TSMC.
On September 12, 2017 Apple announced the Apple A11, a 64-bit ARM-based system on a chip, manufactured by TSMC, using a 10 nm FinFET process and containing 4.3 billion transistors on a die 87.66 square millimetres.
|ITRS Logic Device
|Transistor Fin Pitch (nm)||36||34||42||36|
|Transistor Fin Height||42||53||49||N/A|
|Transistor Gate Pitch (nm)||48||54||68||66|
|Interconnect pitch (nm)||36||36||51||44|
Lower numbers are better. Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch). Samsung reported their 10 nm process as having a 64 nm Transistor Gate Pitch and 48 nm Interconnect Pitch. TSMC reported their 10 nm process as having a 64 nm Transistor Gate Pitch and 42 nm Interconnect Pitch. Further investigation by Tech Insights revealed these values to be false and they have been updated accordingly. In addition, the transistor fin height of Samsung's 10nm process was updated by MSSCORPS CO at SEMICON Taiwan 2017.
|CMOS manufacturing processes||Succeeded by
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