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The Platform Controller Hub (PCH) is a family of Intel microchips, introduced circa 2008. It is the successor to the previous Intel Hub Architecture, which used a northbridge and southbridge instead, and first appeared in the Intel 5 Series.

The PCH controls certain data paths and support functions used in conjunction with Intel CPUs. These include clocking (the system clock), Flexible Display Interface (FDI) and Direct Media Interface (DMI), although FDI is only used when the chipset is required to support a processor with integrated graphics. As such, I/O Functions are reassigned between this new central hub and the CPU compared to the previous architecture: some northbridge functions, the memory controller and PCI-e lanes, were integrated into the CPU while the PCH took over the remaining functions in addition to the traditional roles of the southbridge.

History [edit]

The PCH architecture supersedes Intel's previous Hub Architecture based architecture, and is designed to address the eventual problem of a bottleneck between the processor and the motherboard. The speed of CPU kept increasing, but the bandwidth of the front-side bus (FSB) (connection between the CPU and the motherboard) did not, thus a bottleneck would occur.

Under the hub architecture, a motherboard would have a two piece chipset consisting of a northbridge chip and a southbridge chip. As a solution to the bottleneck, several functions belonging to the traditional northbridge and southbridge chipsets were rearranged. The northbridge is now eliminated completely and its functions, the integrated memory controller (IMC) and graphics lanes, are now incorporated into the CPU die or package.

The PCH then incorporates a few of the remaining northbridge functions (e.g. clocking) in addition to all of the southbridge's functions. The system clock was previously a connection and is now fused in with the PCH. Two different connections exist between the PCH and the CPU: Flexible Display Interface (FDI) and Direct Media Interface (DMI). The FDI is only used when the chipset requires supporting a processor with integrated graphics.

With the northbridge functions integrated to the CPU, much of the bandwidth needed for chipsets is now relieved.

Ibex Peak [edit]

Platform Controller Hub Based Chipset Architecture Block Diagram

The Intel 5 Series chipsets were the first to introduce a PCH. This first PCH is codenamed Ibex Peak.

This has the following variations:

Issues [edit]

  • USB ports hang with bulk and control traffic (erratum 7 & Microsoft KB982091 [1])
  • Bogus USB ports will be detected at desktop PCH equipped with 6 USB ports (3420, H55) on the first EHCI controller. This can happen when AC power is removed after entering ACPI S4. Adding AC power back and resuming from S4 may result in non detected or even non functioning USB device (erratum 12)
  • Bogus USB ports will be detected at mobile PCH equipped with 6 USB ports (HM55) on the first EHCI controller. This can happen when AC power and battery are removed after entering ACPI S4. Adding AC power or battery back and resuming from S4 may result in non detected or even non functioning USB device (erratum 13)
  • Reading the HPET comparator timer immediately after a write, returns the old value (erratum 14)
  • SATA 6Gbit/s devices may not be detected at cold boot or after ACPI S3, S4 resume (erratum 21)

Langwell [edit]

Langwell is the codename of a PCH in the Moorestown MID platform chipset.[1][2] for Atom Lincroft microprocessors.

This has the following variations:

  • AF82MP20 (PCH MP20)
  • AF82MP30 (PCH MP30)

Tiger Point [edit]

Tiger Point is the codename of a PCH in the Pine Trail netbook platform chipset for Atom Pineview microprocessors.

This has the following variations:

Topcliff [edit]

Topcliff is the codename of a PCH in the Queens Bay embedded platform chipset for Atom Tunnel Creek microprocessors.

It connects to the processor via PCI-E (vs. DMI as other PCHs do).

This has the following variations:

Cougar Point [edit]

Cougar Point is the codename of a PCH in Intel 6 Series chipsets for mobile, desktop, and workstation / server platforms. It is most closely associated with Sandy Bridge processors.

This has the following variations:

Issues [edit]

 This section's factual accuracy may be compromised due to out-of-date information. Please help improve the article by updating it. There may be additional information on the talk page. (December 2012)

In the first month of Cougar Point's release, January 2011, Intel posted a press release stating a design error had been discovered.[3] Specifically, a transistor in the 3 Gbit/s PLL clocking tree was receiving too high voltage.[4] The projected result was a 5–15% failure rate within three years of 3 Gbit/s SATA ports, commonly used for storage devices such as hard drives and DVD drives. Through OEMs, Intel plans to repair or replace all affected products at a cost of $700 million.[citation needed]

Whitney Point [edit]

Whitney Point is the codename of a PCH in the Oak Trail platform chipset for Atom Lincroft microprocessors.

This has the following variations:

Panther Point [edit]

Panther Point is the codename of a PCH in Intel 7 Series chipsets for mobile and desktop. It is most closely associated with Ivy Bridge processors. These chipsets have integrated USB 3.0.[5]

This has the following variations:

Patsburg [edit]

Patsburg is the codename of a PCH in Intel 7 Series chipsets for server and workstation. It is most closely associated with Sandy Bridge-E processors in Waimea Bay platforms.[6][7]

This has the following variations:

Future [edit]

Lynx Point is the codename of a future PCH. It is most closely associated with Haswell processors with LGA 1150 socket.[8]

See also [edit]

References [edit]

  1. ^ Langwell Background Information, Intel Corporation, retrieved 2010-08-03 
  2. ^ New Intel Atom Processor-Based Platform Using Significantly Lower Power Readies Intel for Smartphone, Tablet Push, Intel Corporation, May 4, 2010, retrieved 2010-07-27 
  3. ^ Intel Identifies Chipset Design Error, Implementing Solution, Intel, 31 January 2011 
  4. ^ The Source of Intel's Cougar Point SATA Bug, AnandTech, 31 January 2011 
  5. ^ http://www.anandtech.com/show/4406/correction-ivy-bridge-and-thunderbolt-featured-not-integrated
  6. ^ A Look Into Intel's Next Gen Enthusiast Platform : Sandy Bridge E & Waimea Bay, VR-Zone, April, 15 2010, retrieved 2010-07-27 
  7. ^ Intel X58接班人：X79官方规格全曝光-Intel,X58,X79,LGA2011,Sandy Bridge-E,SNB-E-驱动之家, mydrivers.com, 2011-03-30, retrieved 2011-04-17 
  8. ^ http://www.techspot.com/news/50783-leaked-intel-slides-detail-haswells-lynx-point-chipset.html
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