The PCH controls certain data paths and support functions used in conjunction with Intel CPUs. These include clocking (the system clock), Flexible Display Interface (FDI) and Direct Media Interface (DMI), although FDI is only used when the chipset is required to support a processor with integrated graphics. As such, I/O Functions are reassigned between this new central hub and the CPU compared to the previous architecture: some northbridge functions, the memory controller and PCI-e lanes, were integrated into the CPU while the PCH took over the remaining functions in addition to the traditional roles of the southbridge.
The PCH architecture supersedes Intel's previous Hub Architecture based architecture, and is designed to address the eventual problem of a bottleneck between the processor and the motherboard. The speed of CPU kept increasing, but the bandwidth of the front-side bus (FSB) (connection between the CPU and the motherboard) did not, thus a bottleneck would occur.
Under the hub architecture, a motherboard would have a two piece chipset consisting of a northbridge chip and a southbridge chip. As a solution to the bottleneck, several functions belonging to the traditional northbridge and southbridge chipsets were rearranged. The northbridge is now eliminated completely and its functions, the integrated memory controller (IMC) and graphics lanes, are now incorporated into the CPU die or package.
The PCH then incorporates a few of the remaining northbridge functions (e.g. clocking) in addition to all of the southbridge's functions. The system clock was previously a connection and is now fused in with the PCH. Two different connections exist between the PCH and the CPU: Flexible Display Interface (FDI) and Direct Media Interface (DMI). The FDI is only used when the chipset requires supporting a processor with integrated graphics.
With the northbridge functions integrated to the CPU, much of the bandwidth needed for chipsets is now relieved.
Bogus USB ports will be detected at desktop PCH equipped with 6 USB ports (3420, H55) on the first EHCI controller. This can happen when AC power is removed after entering ACPI S4. Adding AC power back and resuming from S4 may result in non detected or even non functioning USB device (erratum 12)
Bogus USB ports will be detected at mobile PCH equipped with 6 USB ports (HM55) on the first EHCI controller. This can happen when AC power and battery are removed after entering ACPI S4. Adding AC power or battery back and resuming from S4 may result in non detected or even non functioning USB device (erratum 13)
Reading the HPET comparator timer immediately after a write, returns the old value (erratum 14)
SATA 6Gbit/s devices may not be detected at cold boot or after ACPI S3, S4 resume (erratum 21)
This section's factual accuracy may be compromised due to out-of-date information. Please update this article to reflect recent events or newly available information.(December 2012)
In the first month of Cougar Point's release, January 2011, Intel posted a press release stating a design error had been discovered. Specifically, a transistor in the 3 Gbit/s PLL clocking tree was receiving too high voltage. The projected result was a 5–15% failure rate within three years of 3 Gbit/s SATA ports, commonly used for storage devices such as hard drives and DVD drives. Through OEMs, Intel plans to repair or replace all affected products at a cost of $700 million.
A design flaw causes devices connected to the Lynx Point's integrated USB 3.0 controller to be disconnected when the system wakes up from the S3 state (Suspend to RAM), forcing the USB devices to be reconnected although no data is lost. This issue is corrected in C2 stepping level of the Lynx Point chipset.