Share
VIDEOS 1 TO 50
Systems on a Chip (SOCs) as Fast As Possible
Systems on a Chip (SOCs) as Fast As Possible
Published: 2016/10/23
Channel: Techquickie
System on Chip (SoC) Explained
System on Chip (SoC) Explained
Published: 2017/03/31
Channel: ALL ABOUT ELECTRONICS
System on a Chip Explained - What is SoC? Smartphone SoC?
System on a Chip Explained - What is SoC? Smartphone SoC?
Published: 2017/12/05
Channel: Technical Guruji
PSoC Lecture 1 ARM Lecture 2 Introduction To SOC Systems On Chip
PSoC Lecture 1 ARM Lecture 2 Introduction To SOC Systems On Chip
Published: 2014/07/23
Channel: Eduvance
Lecture - 10 System On Chip (SOC)
Lecture - 10 System On Chip (SOC)
Published: 2008/04/16
Channel: nptelhrd
Difference between CPU, MPU, MCU, SOC, and MCM?
Difference between CPU, MPU, MCU, SOC, and MCM?
Published: 2017/06/05
Channel: Learning Engineering
zeeSoC - Create your own System-on-a-Chip
zeeSoC - Create your own System-on-a-Chip
Published: 2015/02/28
Channel: Frenoy Osburn
{HINDI} SOC
{HINDI} SOC's or System on chip Explained
Published: 2017/06/14
Channel: PROHIL technical
A Look Inside: SoC FPGAs Introduction (Part 1 of 5)
A Look Inside: SoC FPGAs Introduction (Part 1 of 5)
Published: 2013/11/25
Channel: Intel FPGA
Introduction to PSoC® 4 BLE (Programmable System-on-chip with Bluetooth® Low Energy)
Introduction to PSoC® 4 BLE (Programmable System-on-chip with Bluetooth® Low Energy)
Published: 2014/11/11
Channel: Cypress Semiconductor
System on a chip
System on a chip
Published: 2014/08/27
Channel: Audiopedia
IP-SOC Integration Flow
IP-SOC Integration Flow
Published: 2014/05/07
Channel: ansysinc
#1 DE1-SoC Introduction
#1 DE1-SoC Introduction
Published: 2017/05/05
Channel: Bruce Land
Lecture 10- System On Chip (SOC)
Lecture 10- System On Chip (SOC)
Published: 2013/07/09
Channel: Mubin Sayyed
Chip Timing System Easy To Setup And Use - Orbiter RFID Race Timing
Chip Timing System Easy To Setup And Use - Orbiter RFID Race Timing
Published: 2014/07/01
Channel: OrbiterLLC
[BLU] System on a Chip (SoC): Deep Dive
[BLU] System on a Chip (SoC): Deep Dive
Published: 2014/02/22
Channel: bostonlinuxandunix
Who makes the best SoC: Intel vs Qualcomm vs Samsung
Who makes the best SoC: Intel vs Qualcomm vs Samsung
Published: 2015/12/24
Channel: Android Authority
eRIC  The Power of System on Chip
eRIC The Power of System on Chip
Published: 2013/06/07
Channel: Low Power Radio Solutions Ltd
Snapdragon (system on chip)
Snapdragon (system on chip)
Published: 2014/07/19
Channel: Audiopedia
VLSI Design and System on Chip - SDP
VLSI Design and System on Chip - SDP
Published: 2012/01/21
Channel: adhiyamaaniste
Under The Raspberry Pi CPU: The Actual Soc / CPU
Under The Raspberry Pi CPU: The Actual Soc / CPU
Published: 2015/06/28
Channel: Geek Till It Hertz
SoC(system on chip) and their process....
SoC(system on chip) and their process....
Published: 2015/11/18
Channel: Srivatsa Rao
System On Chip SOC Basics
System On Chip SOC Basics
Published: 2016/03/17
Channel: Castor Classes
Episode 11: Chip Design Flow -- Step 1
Episode 11: Chip Design Flow -- Step 1
Published: 2012/05/16
Channel: Synopsys
$10 Cypress PSoC ARM Cortex-M3 Programmable System-on-Chip
$10 Cypress PSoC ARM Cortex-M3 Programmable System-on-Chip
Published: 2015/03/26
Channel: Charbax
EC-1 - EtherCAT® Dedicated Communication System on Chip
EC-1 - EtherCAT® Dedicated Communication System on Chip
Published: 2016/10/05
Channel: RenesasPresents
Lecture 2: SoC Architecture
Lecture 2: SoC Architecture
Published: 2013/03/14
Channel: Andrei Enescu
Chip Systems Technical service Books with DVDs
Chip Systems Technical service Books with DVDs
Published: 2017/06/24
Channel: Chipsystems in
¿Que es un SOC?
¿Que es un SOC?
Published: 2016/12/07
Channel: B-SECURE
Qualcomm Snapdragon 835 SoC: Explained!
Qualcomm Snapdragon 835 SoC: Explained!
Published: 2017/01/06
Channel: TechDipper
Hackaday semifinals 2015: DIY System on Chip 5 USD
Hackaday semifinals 2015: DIY System on Chip 5 USD
Published: 2015/08/16
Channel: Antti Lukats
How to Remove Reset Button Chip on Continuous Ink System CISS CIS System
How to Remove Reset Button Chip on Continuous Ink System CISS CIS System
Published: 2011/07/02
Channel: SuperToBuy
Waferscale - System On Chip Promotional Video 1998
Waferscale - System On Chip Promotional Video 1998
Published: 2012/07/19
Channel: DatasheetArchiveLtd
System-on-Chip Architecture
System-on-Chip Architecture
Published: 2013/10/30
Channel: Paul Mooney
On-Chip Networks: The Future of SoC Design
On-Chip Networks: The Future of SoC Design
Published: 2013/05/06
Channel: IP WATCH
Episode 185 - 4: System on a Chip - DCC Sunday Seminar Part 4
Episode 185 - 4: System on a Chip - DCC Sunday Seminar Part 4
Published: 2015/01/07
Channel: HamRadioNow
final project for ECE540 System On Chip Design on Nexys4DDR FPGA board.
final project for ECE540 System On Chip Design on Nexys4DDR FPGA board.
Published: 2015/06/12
Channel: Venkat Tulimilli
ARM-based SoC Verification
ARM-based SoC Verification
Published: 2013/03/22
Channel: Mike Bartley
Getting Started with Microsemi SmartFusion2 System on Chip (Part 7) – UART Example
Getting Started with Microsemi SmartFusion2 System on Chip (Part 7) – UART Example
Published: 2016/05/04
Channel: Michael Klopfer
Master
Master's programme in System-on-Chip Design
Published: 2013/06/03
Channel: KTHKista
Intel® Quark™ SoC x1000 | Intel
Intel® Quark™ SoC x1000 | Intel
Published: 2014/04/08
Channel: Intel
FreeBSD on Cavium ThunderX System on a Chip
FreeBSD on Cavium ThunderX System on a Chip
Published: 2016/06/19
Channel: BSDCan
Chipex Car Paint Chip Repair System
Chipex Car Paint Chip Repair System
Published: 2012/03/22
Channel: Chipex
How to Select the Right Programmable System-on-Chip Board For Your Application
How to Select the Right Programmable System-on-Chip Board For Your Application
Published: 2013/01/24
Channel: Future Electronics
Getting Started with Microsemi SmartFusion2 System on Chip (Part 4) – FPGA Fabric Demonstration
Getting Started with Microsemi SmartFusion2 System on Chip (Part 4) – FPGA Fabric Demonstration
Published: 2015/10/05
Channel: Michael Klopfer
Learn How to Build an AHB based ARM SoC (Part 1) HD
Learn How to Build an AHB based ARM SoC (Part 1) HD
Published: 2014/11/21
Channel: Arm
Tutorial:Getting started with FPGA-SoC and Linux Yocto on Terasic DE1-SoC board
Tutorial:Getting started with FPGA-SoC and Linux Yocto on Terasic DE1-SoC board
Published: 2014/11/06
Channel: Toni T800
Innovate with Altera DE1-SoC Board
Innovate with Altera DE1-SoC Board
Published: 2014/01/17
Channel: terasicTV
Stefan Scholl, DC9ST: The Zedboard: A Modern “System On Chip” for SDRs
Stefan Scholl, DC9ST: The Zedboard: A Modern “System On Chip” for SDRs
Published: 2016/03/22
Channel: Software Defined Radio Academy
Assembling Your System on Chip Virtual Prototype With SoC Designer
Assembling Your System on Chip Virtual Prototype With SoC Designer
Published: 2012/04/01
Channel: socvirtualprototype
NEXT
GO TO RESULTS [51 .. 100]

WIKIPEDIA ARTICLE

From Wikipedia, the free encyclopedia
Jump to: navigation, search
The Raspberry Pi uses a system on a chip as an almost fully-contained micro computer. This SoC does not contain any kind of data storage, which is common for microprocessor SoC.

A system on a chip or system on chip (SoC or SOC) is an integrated circuit (also known as an "IC" or "chip") that integrates all components of a computer or other electronic systems. It may contain digital, analog, mixed-signal, and often radio-frequency functions—all on a single substrate. SoCs are very common in the mobile computing market because of their low power consumption.[1] A typical application is in the area of embedded systems.

SoC integrates a microcontroller (or microprocessor) with advanced peripherals like graphics processing unit (GPU), Wi-Fi module, or coprocessor. If the definition of a microcontroller is a system that integrates a microprocessor with peripheral circuits and memory, the SoC is to a microcontroller what a microcontroller is to processors, remembering that the SoC does not necessarily contain built-in memory.

In general, there are three distinguishable types of SoCs. SoCs built around a microcontroller, SoCs built around a microprocessor (this type can be found in mobile phones), and specialized SoCs designed for specific applications that do not fit into the above two categories. A separate category may be Programmable SoC (PSoC), where some of the internal elements are not predefined and can be programmable in a manner analogous to the FPGA or CPLD.

When it is not feasible to construct a SoC for a particular application, an alternative is a system in package (SiP) comprising a number of chips in a single package. When produced in large volumes, SoC is more cost-effective than SiP because its packaging is simpler.[2]

Another option, as seen for example in higher-end cell phones, is package on package stacking during board assembly. The SoC includes processors and numerous digital peripherals, and comes in a ball grid package with lower and upper connections. The lower balls connect to the board and various peripherals, with the upper balls in a ring holding the memory buses used to access NAND flash and DDR2 RAM. Memory packages could come from multiple vendors.

AMD Am286ZX/LX, SoC based on 80286

Structure[edit]

Microcontroller-based system on a chip

A typical SoC consists of:

A bus – either proprietary or industry-standard such as the AMBA bus from ARM Holdings – connects these blocks. DMA controllers route data directly between external interfaces and memory, bypassing the processor core and thereby increasing the data throughput of the SoC.

Design flow[edit]

System-on-a-chip design flow

A SoC consists of both the hardware, described above, and the software controlling the microcontroller, microprocessor or DSP cores, peripherals and interfaces. The design flow for a SoC aims to develop this hardware and software in parallel.

Most SoCs are developed from pre-qualified hardware blocks for the hardware elements described above, together with the software drivers that control their operation. Of particular importance are the protocol stacks that drive industry-standard interfaces like USB. The hardware blocks are put together using CAD tools; the software modules are integrated using a software-development environment.

Once the architecture of the SoC has been defined, any new hardware elements are written in an abstract language termed RTL which defines the circuit behaviour. These elements are connected together in the same RTL language to create the full SoC design.

Chips are verified for logical correctness before being sent to foundry. This process is called functional verification and it accounts for a significant portion of the time and energy expended in the chip design life cycle (although the often quoted figure of 70% is probably an exaggeration).[3] With the growing complexity of chips, hardware verification languages like SystemVerilog, SystemC, e, and OpenVera are being used. Bugs found in the verification stage are reported to the designer.

Traditionally, engineers have employed simulation acceleration, emulation and/or an FPGA prototype to verify and debug both hardware and software for SoC designs prior to tapeout. With high capacity and fast compilation time, acceleration and emulation are powerful technologies that provide wide visibility into systems. Both technologies, however, operate slowly, on the order of MHz, which may be significantly slower – up to 100 times slower – than the SoC's operating frequency. Acceleration and emulation boxes are also very large and expensive at over US$1 million. FPGA prototypes, in contrast, use FPGAs directly to enable engineers to validate and test at, or close to, a system’s full operating frequency with real-world stimuli. Tools such as Certus[4] are used to insert probes in the FPGA RTL that make signals available for observation. This is used to debug hardware, firmware and software interactions across multiple FPGAs with capabilities similar to a logic analyzer.

In parallel, the hardware elements are grouped and passed through a process of logic synthesis, during which performance constraints, such as operational frequency and expected signal delays, are applied. This generates a logical netlist which is a file describing the circuit as a collection of connected silicon gate elements from a library provided by the silicon manufacturer.

This netlist is used as the basis for the physical design (place and route) flow to convert the designers' intent into the polygonal design of the SoC. Throughout this conversion process, the design is analysed with static timing modelling, simulation and other tools to ensure that it meets the specified operational parameters such as frequency, power consumption and dissipation, functional integrity vs. the RTL and electrical integrity.

When all known bugs have been rectified and these have been re-verified and all physical design checks are done, the physical design files describing each layer of the chip are sent to the foundry's mask shop where a full set of glass lithographic masks will be etched. These are sent to the wafer fabrication plant to create the SoC dice before packaging and testing.

Fabrication[edit]

SoCs can be fabricated by several technologies, including:

SoC designs usually consume less power and have a lower cost and higher reliability than the multi-chip systems that they replace. And with fewer packages in the system, assembly costs are reduced as well.

However, like most VLSI designs, the total cost is higher for one large chip than for the same functionality distributed over several smaller chips, because of lower yields and higher non-recurring engineering costs.

Benchmarks[edit]

SoC research and development often compares many options. Benchmarks, such as COSMIC,[5] are developed to help such evaluations.

See also[edit]

References[edit]

  1. ^ Pete Bennett, EE Times. "The why, where and what of low-power SoC design." December 2, 2004. Retrieved July 28, 2015.
  2. ^ EE Times. "The Great Debate: SOC vs. SIP." March 21, 2005. Retrieved July 28, 2015.
  3. ^ EE Times. "Is verification really 70 percent?." June 14, 2004. Retrieved July 28, 2015.
  4. ^ Brian Bailey, EE Times. "Tektronix hopes to shake up ASIC prototyping." October 30, 2012. Retrieved July 28, 2015.
  5. ^ "COSMIC Heterogeneous Multiprocessor Benchmark Suite"

Further reading[edit]

External links[edit]

  • SOCC Annual IEEE International SOC Conference
  • Baya free SoC platform assembly and IP integration tool

Disclaimer

None of the audio/visual content is hosted on this site. All media is embedded from other sites such as GoogleVideo, Wikipedia, YouTube etc. Therefore, this site has no control over the copyright issues of the streaming media.

All issues concerning copyright violations should be aimed at the sites hosting the material. This site does not host any of the streaming media and the owner has not uploaded any of the material to the video hosting servers. Anyone can find the same content on Google Video or YouTube by themselves.

The owner of this site cannot know which documentaries are in public domain, which has been uploaded to e.g. YouTube by the owner and which has been uploaded without permission. The copyright owner must contact the source if he wants his material off the Internet completely.

Powered by YouTube
Wikipedia content is licensed under the GFDL and (CC) license