||This article's lead section may not adequately summarize key points of its contents. (May 2014)|
One of the first Z80 microprocessors manufactured; the date stamp is from June 1976.
|Produced||From 1976 to present|
The Zilog Z80 is an 8-bit microprocessor designed by Zilog and sold from July 1976 onwards. It was widely used both in desktop and embedded computer designs as well as for military purposes. The Z80 and its derivatives and clones made up one of the most commonly used CPU families of all time, and, along with the MOS Technology 6502 family, dominated the eight-bit microcomputer market from the late 1970s to the mid-1980s.
Zilog licensed the Z80 design to several vendors, though many East European (for instance, Russian) manufacturers made unlicensed copies. This enabled a small company's product to gain acceptance in the world market since second sources from far larger companies such as Toshiba started to manufacture the device. Consequently, Zilog has made less than 50% of the Z80s since its conception. In recent decades Zilog has refocused on the ever-growing market for embedded systems (for which the original Z80 and the Z180 were designed) and the most recent Z80-compatible microcontroller family, the fully pipelined 24-bit eZ80 with a linear 16 MB address range, has been successfully introduced alongside the simpler Z180 and Z80 products.
The Z80 came about when Federico Faggin, after working on the 8080, left Intel at the end of 1974 to found Zilog with Ralph Ungermann, and by July 1976 they had the Z80 on the market. It was designed to be binary compatible with the Intel 8080 so that most 8080 code, notably the CP/M operating system, would run unmodified on it. Masatoshi Shima, co-designer of the 4004 and the 8080, also contributed to the development of the Z80.
The Z80 offered many improvements over the 8080:
The Z80 took over from the 8080 and its offspring, the 8085, in the processor market, and became one of the most popular 8-bit CPUs. Perhaps a key to the initial success of the Z80 was the built-in DRAM refresh, and other features which allowed systems to be built with fewer support chips (later on, most Z80 systems have been embedded systems, which typically uses static RAM and hence does not need this refresh).
For the original NMOS design, the specified upper clock frequency limit increased successively from the introductory 2.5 MHz, via the well known 4 MHz (Z80A), up to 6 (Z80B) and 8 MHz (Z80H). A CMOS version was also developed with specified frequency limits ranging from 4 MHz up to 20 MHz for the version sold today. The CMOS version also allowed a low-power sleep with internal state retained (having no lower frequency limit). The fully compatible derivatives HD64180/Z180 and eZ80 are currently specified for up to 33 and 50 MHz respectively.
The programming model and register set are conventional and similar to the related x86 family. The 8080 compatible registers AF, BC, DE, HL are duplicated as two separate banks in the Z80, where the processor can quickly switch from one bank to the other; a feature useful for speeding up responses to single-level, high-priority interrupts. This feature was present in the Datapoint 2200 but was not implemented by Intel in the 8008. The dual register-set makes sense as the Z80 (like most microprocessors at the time) was really intended for embedded use, not for personal computers, or the yet-to-be invented home computers. According to one of the designers, Masatoshi Shima, the market focus was on high performance printers, high-end cash registers, and intelligent terminals. The two register sets also turned out to be quite useful for heavily optimized manual assembly-language coding. Some software, especially games for the MSX, Sinclair ZX Spectrum and other Z80 based computers, took Z80 assembly optimization to rather extreme levels, employing the duplicated registers among other things to squeeze maximum performance out of the processor.
|The Z80 registers|
As on the 8080, 8-bit registers are typically coupled to provide 16-bit versions. The 8080 compatible registers are:
AF: 8-bit accumulator (A) and flag bits (F) carry, zero, minus, parity/overflow, half-carry (used for BCD), and an Add/Subtract flag (usually called N) also for BCD
BC: 16-bit data/address register or two 8-bit registers
DE: 16-bit data/address register or two 8-bit registers
HL: 16-bit accumulator/address register or two 8-bit registers
SP: stack pointer, 16 bits
PC: program counter, 16 bits
The new registers introduced with the Z80 are:
IX: 16-bit index or base register for 8-bit immediate offsets
IY: 16-bit index or base register for 8-bit immediate offsets
I: interrupt vector base register, 8 bits
R: DRAM refresh counter, 8 bits (msb does not count)
AF': alternate (or shadow) accumulator and flags (toggled in and out with EX AF,AF' )
HL': alternate (or shadow) registers (toggled in and out with EXX)
There is no direct access to the alternate registers; instead, two special instructions,
EX AF,AF' and
EXX, each toggles one of two multiplexer flip-flops; this enables fast context switches for interrupt service routines:
EX AF, AF' may be used alone (for really simple and fast interrupt routines) or together with
EXX to swap the whole BC, DE, HL set; still much faster than pushing the same registers on the stack (slower, lower priority, or multi level interrupts normally use the stack to store registers).
The refresh register,
R, increments each time the CPU fetches an opcode (or opcode prefix) and has therefore no simple relationship with program execution. This has sometimes been used to generate pseudorandom numbers in games, and also in software protection schemes. It has also been employed as a "hardware" counter in some designs; an example of this is the ZX81, which lets it keep track of character positions on the TV screen by triggering an interrupt at wrap around (by connecting INT to A6).
The interrupt vector register,
I, is used for the Z80 specific mode 2 interrupts (selected by the
IM 2 instruction). It supplies the high byte of the base address for a 128-entry table of service routine addresses which are selected via an index sent to the CPU during an interrupt acknowledge cycle; this index is simply the low byte part of the pointer to the tabulated indirect address pointing to the service routine. The pointer identifies a particular peripheral chip and/or peripheral function or event, where the chips are normally connected in a so-called daisy chain for priority resolution. Like the refresh register, this register has also sometimes been used creatively; in interrupt modes 0 and 1 it can be used as simply another 8-bit data register.
The first Intel 8008 assembly language was based on a very simple (but systematic) syntax inherited from the Datapoint 2200 design. This original syntax was later transformed into a new, somewhat more traditional, assembly language form for this same original 8008 chip. At about the same time, the new assembly language was also extended to accommodate the added addressing possibilities in the more advanced Intel 8080 chip (the 8008 and 8080 shared a language subset without being binary compatible; however, the 8008 was binary compatible with the Datapoint 2200).
In this process, the mnemonic
L, for LOAD, was replaced by various abbreviations of the words LOAD, STORE and MOVE, intermixed with other symbolic letters. The mnemonic letter
M, for memory (referenced by HL), was lifted out from within the instruction mnemonic to become a syntactically freestanding operand, while registers and combinations of registers became very inconsistently denoted; either by abbreviated operands (MVI D, LXI H and so on), within the instruction mnemonic itself (LDA, LHLD and so on), or both at the same time (LDAX B, STAX D and so on).
|Datapoint 2200 & i8008||i8080||Z80||i8086/i8088|
|LBC||MOV B,C||LD B,C||MOV BL,CL||put the value in the C register in the B register|
|--||LDAX B||LD A,(BC)||MOV AL,[BX]||put the value in the address pointed to by the BC register in the A register|
|LAM||MOV A,M||LD A,(HL)||MOV AL,[BP]||put the value in the address pointed to by the HL register in the A register|
|LBM||MOV B,M||LD B,(HL)||MOV BL,[BP]||put the value in the address pointed to by the HL register in the B register|
|--||STAX D||LD (DE),A||MOV [DX],AL||put the value in the A register in the address pointed to by the DE register|
|LMA||MOV M,A||LD (HL),A||MOV [BP],AL||put the value in the A register in the address pointed to by the HL register|
|LMC||MOV M,C||LD (HL),C||MOV [BP],CL||put the value in the C register in the address pointed to by the HL register|
|LDI 56||MVI D,56||LD D,56||MOV DL,56||put the value 56 in the D register|
|LMI 56||MVI M,56||LD (HL),56||MOV byte ptr [BP],56||put the value 56 in the address pointed to by the HL register|
|--||LDA 1234||LD A,(1234)||MOV AL,||put the value in address 1234 in the A register|
|--||STA 1234||LD (1234),A||MOV ,AL||put the value in the A register in address 1234|
|--||--||LD B,(IX+56)||MOV BL,[SI+56]||put the value in the (base) address pointed to by the IX register +56 (offset) in the B register|
|--||--||LD (IX+56),C||MOV [SI+56],CL||put the value in the C register in the address pointed to by the SI register +56 (offset)|
|--||--||LD (IY+56),78||MOV byte ptr [DI+56],78||put the value 78 in the address pointed to by the IY register +56 (offset)|
|--||LXI B,1234||LD BC,1234||MOV BX,1234||put the value 1234 in the BC register|
|--||LXI H,1234||LD HL,1234||MOV BP,1234||put the value 1234 in the HL register|
|--||SHLD 1234||LD (1234),HL||MOV ,BP||put the value in the HL register in address 1234|
|--||LHLD 1234||LD HL,(1234)||MOV BP,||put the value in address 1234 in the HL register|
|--||--||LD BC,(1234)||MOV BX,||put the value in address 1234 in the BC register|
|--||--||LD IX,(1234)||MOV SI,||put the value in address 1234 in the IX register|
Illustration of four syntaxes, using samples of equivalent, or (for 8086) very similar, load and store instructions.
Because Intel had a copyright on their assembly mnemonics, a new assembly syntax had to be developed for the Z80. This time a more systematic approach was used:
These principles made it straightforward to find names and forms for all new Z80 instructions, as well as orthogonalizations of old ones, such as
Apart from naming differences, and despite a certain discrepancy in basic register structure, the Z80 and 8086 syntax are virtually isomorphous for a large portion of instructions. Only quite superficial similarities (such as the word MOV, or the letter X, for extended register) exist between the 8080 and 8086 assembly languages, although 8080 programs can be assembled into 8086 object code using a special assembler or translated to 8086 assembly language by a translator program.
The Z80 uses 252 out of the available 256 codes as single byte opcodes ("root instruction"); the four remaining codes are used extensively as opcode prefixes: CB and ED enable extra instructions and DD or FD selects IX+d or IY+d respectively (in some cases without displacement d) in place of HL. This scheme gives the Z80 a large number of permutations of instructions and registers; Zilog categorizes these into 158 different "instruction types", 78 of which are the same as those of the Intel 8080 (allowing operation of 8080 programs on a Z80). The Zilog documentation further groups instructions into the following categories:
No multiply instruction is available in the original Z80. Different sizes and variants of additions, shifts, and rotates have somewhat differing effects on flags because the flag-influencing properties of the 8080 were copied. Load instructions do not affect the flags (except for the special purpose I and R register loads).
The index register (IX/IY) instructions can be useful for accessing data organised in fixed heterogenous structures (such as records) or at fixed offsets relative a variable base address (as in recursive stack frames) and can also reduce code size by removing the need for multiple short instructions using non-indexed registers. However, although they may save speed in some contexts when compared to long/complex "equivalent" sequences of simpler operations, they incur a lot of additional CPU time (e.g. 19 T-states to access one indexed memory location vs. as little as 11 to access the same memory using HL and INCrement it to point to the next). Thus, for simple or linear accesses of data, IX and IY tend to be slower. Still, they may be useful in cases where the 'main' registers are all occupied, by removing the need to save/restore registers. Their officially undocumented 8-bit halves (see below) can be especially useful in this context, for they incur less slowdown than their 16-bit parents. Similarly, instructions for 16-bit additions are not particularly fast (11 clocks) in the original Z80; nonetheless, they are about twice as fast as performing the same calculations using 8-bit operations, and equally important, they reduce register usage.
The 10-year-newer microcoded Z180 design could initially afford more "chip area", permitting a slightly more efficient implementation (using a wider ALU, among other things); similar things can be said for the Z800, Z280, and Z380. However, it was not until the fully pipelined eZ80 was launched in 2001 that those instructions finally became approximately as cycle-efficient as it is technically possible to make them, i.e. given the Z80 encodings combined with the capability to do an 8-bit read or write every clock cycle.
The index registers, IX and IY, were intended as flexible 16 bit pointers, enhancing the ability to manipulate memory, stack frames and data structures. Officially, they were treated as 16-bit only. In reality, they were implemented as a pair of 8-bit registers, in the same fashion as the HL register, which is accessible either as 16 bits or separately as the High and Low registers. Even the binary opcodes (machine language) were identical, but preceded by a new opcode prefix. Zilog published the opcodes and related mnemonics for the intended functions, but did not document the fact that every opcode that allowed manipulation of the H and L registers was equally valid for the 8 bit portions of the IX and IY registers. As an example, the opcode 26h followed by an immediate byte value (LD H,n) will load that value into the H register. Preceding this two-byte instruction with the IX register's opcode prefix, DD, would instead result in the most significant 8 bits of the IX register being loaded with that same value. A notable exception to this would be instructions similar to LD H,(IX+d) which make use of both the HL and IX or IY registers in the same instruction; in this case the DD prefix is only applied to the (IX+d) portion of the instruction.
There are several other undocumented instructions as well. Undocumented or illegal opcodes are not detected by the Z80 and have various effects, some of which are useful. However, as they are not part of the formal definition of the instruction set, different implementations of the Z80 are not guaranteed to work the same way for every undocumented opcode.
The following Z80 assembly source code is for a subroutine named
memcpy that copies a block of data bytes of a given size from one location to another. Important: The example code does not handle a certain case where the destination block overlaps the source; a fatal bug. The sample code is extremely inefficient, intended to illustrate various instruction types, rather than best practices for speed. In particular the Z80 has a single instruction that will execute the entire loop (
LDIR). The data block is copied one byte at a time, and the data movement and looping logic utilizes 16-bit operations. Note that the assembled code is binary-compatible with the Intel 8080 and 8085 CPUs.
; memcpy -- ; Copy a block of memory from one location to another. ; ; Entry registers ; BC - Number of bytes to copy ; DE - Address of source data block ; HL - Address of target data block ; ; Return registers ; BC - Zero 1000 org 1000h ;Origin at 1000h 1000 memcpy public 1000 78 loop ld a,b ;Test BC, 1001 B1 or c ;If BC = 0, 1002 C8 retz ;Return 1003 1A ld a,(de) ;Load A from (DE) 1004 77 ld (hl),a ;Store A into (HL) 1005 13 inc de ;Increment DE 1006 23 inc hl ;Increment HL 1007 0B dec bc ;Decrement BC 1008 C3 00 10 jp loop ;Repeat the loop 100B end
Each instruction is executed in steps that are usually termed machine cycles (M-cycles), each of which can take between three and six clock periods (T-cycles). Each M-cycle corresponds roughly to one memory access and/or internal operation. Many instructions actually end during the M1 of the next instruction which is known as a fetch/execute overlap.
|4||SET b,(HL)||prefix||opcode||R(HL), set||W(HL)|
The Z80 machine cycles are sequenced by an internal state machine which builds each M-cycle out of 3, 4, 5 or 6 T-cycles depending on context. This avoids cumbersome asynchronous logic and makes the control signals behave consistently at a wide range of clock frequencies. It also means that a higher frequency crystal must be used than without this subdivision of machine cycles (approximately 2–3 times higher). It does not imply tighter requirements on memory access times, however, as a high resolution clock allows more precise control of memory timings and memory therefore can be active in parallel with the CPU to a greater extent (i.e. sitting less idle), allowing more efficient use of available memory bandwidth.
One central example of this is that, for opcode fetch, the Z80 combines two full clock cycles into a memory access period (the M1-signal). In the Z80 this signal therefore lasts for a much larger (relative) part of the typical instruction execution time than in a more asynchronous processor design such as the 6800, 6502, or similar, where this period would typically last only a (rather inprecise) fraction (typically 30-40%) of a clock cycle. With memory chip affordability (i.e. access times around 450-250 ns in the 1980s) typically determining the fastest possible access time, this meant that such designs were locked to a significantly longer clock cycle (i.e. lower internal clock speed) than the Z80.
Memory, especially EPROM, but also Flash, were generally slow as compared to the state machine sub-cycles (clock cycles) used in contemporary microprocessors. The shortest machine cycle that could safely be used in embedded designs has therefore often been limited by memory access times, not by the maximum CPU frequency (especially so during the home computer era). However, this relation has slowly changed during the last decades, particularly regarding SRAM; cacheless, single-cycle designs such as the eZ80 have therefore become much more meaningful recently.
Zilog introduced a number of peripheral parts for the Z80, which all supported the Z80's interrupt handling system and I/O address space. These included the Counter/Timer Channel (CTC), the SIO (Serial Input Output), the DMA (Direct Memory Access), the PIO (Parallel Input-Output) and the DART (Dual Asynchronous Receiver Transmitter). As the product line developed, low-power, high-speed and CMOS versions of these chips were produced.
Like the 8080, 8085 and 8086 processors, but unlike processors such as the Motorola 6800 and MOS Technology 6502, the Z80 and 8080 had a separate control line and address space for I/O instructions. While some Z80-based computers such as the Osborne 1 used "Motorola-style" memory mapped input/output devices, usually the I/O space was used to address one of the many Zilog peripheral chips compatible with the Z80. Zilog I/O chips supported the Z80's new mode 2 interrupts which simplified interrupt handling for large numbers of peripherals.
The Z80 was officially described as supporting 16-bit (64 KB) memory addressing, and 8-bit (256 ports) I/O-addressing. All I/O instructions actually assert the entire 16-bit address bus. OUT (C),reg and IN reg,(C) places the contents of the entire 16 bit BC register on the address bus; OUT (n),A and IN A,(n) places the contents of the A register on b8-b15 of the address bus and n on b0-b7 of the address bus. A designer could choose to decode the entire 16 bit address bus on I/O operations in order to take advantage of this feature, or use the high half of the address bus to select subfeatures of the I/O device. This feature has also been used to minimise decoding hardware requirements, such as in the Amstrad CPC/PCW and ZX81.
Mostek, who produced the first Z80 for Zilog, offered it as second-source as MK3880. SGS-Thomson (now STMicroelectronics) was a second-source, too, with their Z8400. Sharp and NEC developed second sources for the NMOS Z80, the LH0080 and µPD780C respectively. The µPD780C was used in the Sinclair ZX80 and ZX81, original versions of the ZX Spectrum, and several MSX computers, and in musical synthesizers such as Oberheim OB-8 and others. The LH0080 was used in various home computers and personal computers made by Sharp and other Japanese manufacturers, including Sony MSX computers, and a number of computers in the Sharp MZ series.
Toshiba made a CMOS-version, the TMPZ84C00, which is believed[by whom?] (but not verified) to be the same design also used by Zilog for its own CMOS Z84C00. There were also Z80-chips made by GoldStar (alias LG) and the BU18400 series of Z80-clones (including DMA, PIO, CTC, DART and SIO) in NMOS and CMOS made by ROHM Electronics.
In East Germany, an unlicensed clone of the Z80, known as the U880, was manufactured. It was very popular and was used in Robotron's and VEB Mikroelektronik Mühlhausen's computer systems (such as the KC85-series) and also in many self-made computer systems (such as COMP JU+TER). In Romania another unlicensed clone could be found, named MMN80CPU and produced by Microelectronica, used in home computers like TIM-S, HC, COBRA.
Also, several clones of Z80 were created in the Soviet Union, notable ones being the T34BM1, also called КР1858ВМ1 (parallelling the Russian 8080-clone KR580VM80A) The first marking was used in pre-production series, while the second had to be used for a larger production. Though, due to the collapse of Soviet microelectronics in the late 1980s, there are many more T34BM1s than КР1858ВМ1s.
During the late 1970s and early 1980s, the Z80 was used in a great number of fairly anonymous business-oriented machines with the CP/M operating system, a combination that dominated the market at the time. Two well-known examples of Z80+CP/M business computers are the portable Osborne 1 and the Kaypro series. Research Machines manufactured the 380Z and 480Z microcomputers which were networked with a thin Ethernet type LAN and CP/NET in 1981. Other manufacturers of such systems included Televideo, Xerox (820 range) and a number of more obscure firms. Some systems used multi-tasking operating system software to share the one processor between several concurrent users.
In the U.S., the Radio Shack TRS-80, introduced in 1977, as well as the Models II, III, IV, and the proposed Model V, used the Z80. In the United Kingdom, Sinclair Research used the Z80 and Z80A in its ZX80, ZX81 and, ZX Spectrum home computers. Amstrad used them in their Amstrad CPC range and an early UK computer, the Nascom 1 and 2 also used the Z80. The Commodore 128 featured a Z80 processor alongside its MOS Technology 8502 processor for CP/M compatibility. Other 6502 architecture computers on the market at the time, such as the BBC Micro, Apple II, and the 6510 based Commodore 64, could make use of the Z80 with an external unit, a plug-in card, or an expansion ROM cartridge. The Microsoft Z-80 SoftCard for the Apple II was a particularly successful add-on card and one of Microsoft's few hardware products of the era.
In 1981, Multitech (later to become Acer) introduced the Microprofessor I, a simple and inexpensive training system for the Z80 microprocessor. Currently, it is still manufactured and sold by Flite Electronics International Limited in Southampton, England.
||This section is in a list format that may be better presented using prose. (May 2014)|
The Zilog Z80 has long been a popular microprocessor in embedded systems and microcontroller cores, where it remains in widespread use today. The following list provides examples of such applications of the Z80, including uses in consumer electronics products.
In the 8-bit world, the two most popular microcomputers are the Z80 and 6502 computer chips.
The register architecture of the Z80 is more innovative than that of the 8085
interrupt processing commences according to the interrupt method stipulated by the IM i, i=0, 1, or 2, instruction. If i=1, for direct method, the PC is loaded with 0038H. If i=0, for vectored method, the interrupting device has the opportunity to place the op-code for one byte . If i=2, for indirect vector method, the interrupting device must then place a byte . The Z80 then uses this byte where one of 128 interrupt vectors can be selected by the byte .
In addition to supporting the entire Z80 instruction set, the Z180
The designers picked an architecture compatible with the Z80, giving Z80 users a completely software compatible upgrade path. The 64180 processor runs every Z80 instruction exactly as a Z80 does
All mnemonics copyright Intel Corporation 1977
JP) instructions, which load the program counter with a new instruction address, do not themselves access memory. Absolute and relative forms of the jump reflect this by omitting the round brackets from their operands. Register based jump instructions such as "
JP (HL)" include round brackets in an apparent deviation from this convention."Z80 Relocating Macro Assembler User's Guide" (PDF). p. Page B–2.
The 8086 is software-compatible with the 8080 at the assembly-language level.
An Intel translator program could convert 8080 assembler programs into 8086 assembler programs
It has a language of 252 root instructions and with the reserved 4 bytes as prefixes, accesses an additional 308 instructions.
The 8-bit microprocessors that preceded the 80x86 family (such as the Intel 8080, the Zilog Z80, and the Motorola) did not include multiplication.
Undocumented Z80 codes allow 8 bit operations with IX and IY registers.
If an opcode works with the registers HL, H or L then if that opcode is preceded by #DD (or #FD) it works on IX, IXH or IXL (or IY, IYH, IYL), with some exceptions. The exceptions are instructions like LD H,IXH and LD L,IYH
ADD A, n Add accumulator with immediate data n. MEMORY Timing: 2 M cycles; 7 T states.
The I/O instructions use the whole of the address bus, not just the lower 8 bits. So in fact, you can have 65536 I/O ports in a Z80 system (the Spectrum uses this). IN r,(C), OUT (C),r and all the I/O block instructions put the whole of BC on the address bus. IN A,(n) and OUT (n),A put A*256+n on the address bus.
Most MZ's use the 8bit CPU LH0080 / Z80 [...]
The 64180 is a Hitachi-supplied Z80 core with numerous on-chip "extras". Zilog's version is the Z180, which is essentially the same part.
Both Toshiba and Zilog sell the 84013 and 84015, which are Z80 cores with conventional Z80 peripherals integrated on-board.
Kawasaki's KL5C80A12, KL5C80A16 and KL5C8400 are high speed 8-bit MCUs and CPU. Their CPU code, KC80 is compatible with Zilog's Z80 at binary level. KC80 executes instructions about four times faster than Z80 at the same clock rate
Rabbit Semiconductor's Rabbit 3000 microprocessor, which is a much improved and enhanced derivative of ZiLOG, Inc.'s venerable Z80 microprocessor.
The Rabbit parts are based closely on the Zilog Z180 architecture, although they are not binary compatible with the Zilog parts.
and CP/M continued to dominate the 8-bit world of microcomputers.
The idea of a generic operating system is still in its infancy. In many ways it begins with CP/M and the mishmash of early 8080 and Z80 computers.
C-128 CP/M uses both the Z80 and 8502 processors. The Z80 executes most of the CP/M BIOS functions.
Several manufacturers, however, make Z80 coprocessor boards that plug into the Apple II.
The Commodore 64 CP/M package contains a plug-in cartridge with a Z80 microprocessor and the CP/M operating system on a disk.
The Intoxilyzer 5000EN, a breathalyzer, runs on a pair of Z80 processors
The ColecoVision uses the Z80 microprocessorMissing or empty
Internally, both the NES and Master System were equipped with 8-bit processors (a 6502 and a Zilog Z80, respectively)
Although the Prophet 5s and Prophet 10s incorporated Z80 microprocessors,
CPU is Z80 + Z80CTC
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